This application claims the priority benefit of Taiwan application Ser. No. 91100281, filed Jan. 11, 2002.
1. Field of Invention
The present invention relates to a test structure and a test method. More particularly, the present invention relates to a test structure and a test method for a flash memory.
2. Description of Related Art
The flash memory is a type of electrically erasable programmable ROM (EEPROM), which has advantages of writing, erasing, and data remaining after power being off, and is a memory device widely used in various personal computer and electronic equipment. Moreover, the flash memory is also a type of non-volatile memory, which has advantages of small dimension, high access speed, and low power consumption. In addition, since the data erasing operation is done in a manner of block by block, the operation speed is faster.
Since the quality of tunneling oxide layer of the flash memory device would affect the lifetime of the flash memory device, a test process usually is performed after the flash memory device has been done. This is to test the quality of the tunneling oxide layer and then predict the lifetime of the tunneling oxide layer.
FIG. 1 is a top view, schematically illustrating a test device for the tunneling oxide layer of the flash memory device.
In FIG. 1, the conventional test device 100 includes a control gate electrode 101, a floating gate electrode 102, a tunneling oxide layer (not seen), a diffusion region 104, and several contact 106.
The floating gate electrode 102 is disposed on the diffusion region 104. The control gate electrode 101 is disposed on the floating gate electrode 102. The tunneling oxide layer is disposed between the floating gate electrode 102 and the diffusion region 104. Several contact structures 106 are disposed along one side of the floating gate electrode 102, in which the contact structures are electrically connected through a metal line 108.
The conventional method for testing the quality of the tunneling oxide layer is that a voltage is applied on the metal line 108 of the conventional test device 100. Then, a testing result is obtained, so as to predict the lifetime of the tunneling oxide layer.
FIG. 2 is a drawing, illustrating a voltage distribution resulted from the test method on the conventional test device.
In FIG. 2, the X axis and Y axis respectively indicate the position where is the test is done. The Z axis in FIG. 2 represents the quantity of the measured voltage in volt. According to the voltage distribution in FIG. 2, when the convention test device is used to test the tunneling oxide layer of the flash memory, the distribution of voltage drop clearly is not uniform. This would result in non-uniform distribution of tunneling current, which flows through the tunneling oxide layer.
The reasons to cause the non-uniform distribution of the voltage drop and the tunneling current is that the contact structures of the conventional test device are only disposed along one side of the floating gate electrode. In this manner, the voltage drop only occurs at the regions, which have the contact structures. For this situation, the testing results can only reflect the quality with respect to the side portion. The quality of the tunneling oxide located at the other sides and the central portion is then ignored. Thus, it has poor precision of test result and low reliability for the test method performed on the test device.
Moreover, since the conventional test device is used for test on the floating gate electrode with a rather larger area, the floating gate electrode has larger sheet resistance, resulting in that the testing result is usually better than the actual quality.
Furthermore, since the conventional test device has only one row of contact structures, disposed along one side, it will cause a non-uniform distribution of voltage drop and tunneling current during the testing procedure. The non-uniform distribution of voltage drop and tunneling current would result in a better testing result than the actual quality. In this situation, the test device associating with the test method cannot provide a precise testing result with reliability.
It is an object of the invention to provide a test structure and a test method for a flash memory, so as to avoid the non-uniform distribution of voltage drop and tunneling current, which occurs in the convention method.
It is another object of the invention to provide a test structure and a test method for a flash memory, so as to more precisely predict the lifetime of the tunneling oxide, and thereby improve the reliability of the testing result.
As embodied and broadly described herein, the invention provides a method for testing a tunneling oxide layer of a flash memory. The method includes providing a test device. The test device includes a diffusion region, a floating gate electrode above the diffusion region, and a tunneling oxide layer disposed between the diffusion region and the floating gate electrode. In addition, a number of contacts over the floating gate electrode are disposed along a peripheral region of the test device. It has no a diffusion region under a portion of the floating gate electrode, which has the floating-gate contacts. In addition, a number of diffusion-region contacts are disposed over the diffusion region. Between the floating-gate contacts are electrically connected through a first metal line. The diffusion-region contacts are electrically connected by a second metal line. Then, a first voltage is applied to the floating-gate contacts and a second voltage is applied on to the diffusion-region contacts.
The invention also provides a test device for use on testing a tunneling oxide layer. The test device includes a diffusion region, a tunneling oxide layer, a floating gate electrode, a number of floating-gate contacts, and a number of diffusion-region contacts. The floating gate electrode is disposed above the diffusion region. The tunneling oxide layer is disposed between the diffusion region and the floating gate electrode. The floating-gate contacts are disposed along the periphery of the floating gate electrode. It has no the diffusion region below a portion of the floating gate electrode with the floating-gate contacts. The diffusion-region contacts are disposed at the periphery of the diffusion region. The test device of the invention has, for example, a gear-like structure along the periphery, wherein an indent region exposes a portion of tunneling oxide layer above the diffusion layer. The diffusion-region contacts are disposed within the indent region of the gear-like structure. In addition, diffusion-region contacts are also disposed at the interior region of the test device, that is, the interior region of the floating gate electrode. The diffusion-region contacts expose the diffusion region and form a net-like structure. Moreover, the test device of the invention further includes a first conductive line and a second conductive line. The first conductive line is disposed over the floating-gate contacts, so as to electrically connect each together. The second conductive line is disposed over the diffusion-region contacts, so as to electrically connected together.
The test device and the method for testing the tunneling oxide layer of the flash memory include the contacts, which are evenly distributed over the test device at the periphery and the interior region. As a result, during testing, the voltage drop and the tunneling current can be more uniform. Therefore, the precision of the testing result and reliability are improved.
The difference of the test device for testing the tunneling oxide layer of the flash memory in the invention is including the design of diffusion-region openings. When the test device is under the test by perform a Qbd measurement, which accumulate the breakdown voltage, the voltage can be set to be substantially equal to the voltage needed by the flash memory for Negative Gate Source-side Erase (NGSE).